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7120742701
Now that we have moved WebRTC from src/webrtc to src/, common_types.h and typedefs.h are triggering a cpplint error. The cpplint complaint is: Include the directory when naming .h files [build/include] [4] This CL disables the error but we have to remove these two headers from the root directory. NOPRESUBMIT=true Bug: webrtc:5876 Change-Id: I08e1b69aadcc4b28ab83bf25e3819d135d41d333 Reviewed-on: https://webrtc-review.googlesource.com/1577 Commit-Queue: Mirko Bonadei <mbonadei@webrtc.org> Reviewed-by: Henrik Kjellander <kjellander@google.com> Reviewed-by: Karl Wiberg <kwiberg@webrtc.org> Cr-Commit-Position: refs/heads/master@{#19859}
329 lines
18 KiB
C
329 lines
18 KiB
C
/*
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* Copyright (c) 2014 The WebRTC project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <stddef.h>
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#include "modules/audio_coding/codecs/isac/fix/source/settings.h"
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#include "typedefs.h" // NOLINT(build/include)
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// Filter ar_g_Q0[] and ar_f_Q0[] through an AR filter with coefficients
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// cth_Q15[] and sth_Q15[].
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void WebRtcIsacfix_FilterArLoop(int16_t* ar_g_Q0, // Input samples
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int16_t* ar_f_Q0, // Input samples
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int16_t* cth_Q15, // Filter coefficients
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int16_t* sth_Q15, // Filter coefficients
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size_t order_coef) { // order of the filter
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int n = 0;
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for (n = 0; n < HALF_SUBFRAMELEN - 1; n++) {
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int count = (int)(order_coef - 1);
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int offset;
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#if !defined(MIPS_DSP_R1_LE)
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int16_t* tmp_cth;
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int16_t* tmp_sth;
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int16_t* tmp_arg;
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int32_t max_q16 = 0x7fff;
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int32_t min_q16 = 0xffff8000;
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#endif
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// Declare variables used as temporary registers.
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int32_t r0, r1, r2, t0, t1, t2, t_ar;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"bltz %[count], 2f \n\t"
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" lh %[t_ar], 0(%[tmp]) \n\t"
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// Inner loop
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"1: \n\t"
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"sll %[offset], %[count], 1 \n\t"
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#if defined(MIPS_DSP_R1_LE)
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"lhx %[r0], %[offset](%[cth_Q15]) \n\t"
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"lhx %[r1], %[offset](%[sth_Q15]) \n\t"
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"lhx %[r2], %[offset](%[ar_g_Q0]) \n\t"
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#else
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"addu %[tmp_cth], %[cth_Q15], %[offset] \n\t"
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"addu %[tmp_sth], %[sth_Q15], %[offset] \n\t"
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"addu %[tmp_arg], %[ar_g_Q0], %[offset] \n\t"
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"lh %[r0], 0(%[tmp_cth]) \n\t"
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"lh %[r1], 0(%[tmp_sth]) \n\t"
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"lh %[r2], 0(%[tmp_arg]) \n\t"
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#endif
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"mul %[t0], %[r0], %[t_ar] \n\t"
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"mul %[t1], %[r1], %[t_ar] \n\t"
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"mul %[t2], %[r1], %[r2] \n\t"
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"mul %[r0], %[r0], %[r2] \n\t"
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"subu %[t0], %[t0], %[t2] \n\t"
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"addu %[t1], %[t1], %[r0] \n\t"
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#if defined(MIPS_DSP_R1_LE)
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"shra_r.w %[t1], %[t1], 15 \n\t"
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"shra_r.w %[t0], %[t0], 15 \n\t"
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#else
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"addiu %[t1], %[t1], 0x4000 \n\t"
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"sra %[t1], %[t1], 15 \n\t"
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"addiu %[t0], %[t0], 0x4000 \n\t"
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"sra %[t0], %[t0], 15 \n\t"
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#endif
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"addiu %[offset], %[offset], 2 \n\t"
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#if defined(MIPS_DSP_R1_LE)
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"shll_s.w %[t1], %[t1], 16 \n\t"
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"shll_s.w %[t_ar], %[t0], 16 \n\t"
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#else
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"slt %[r0], %[t1], %[max_q16] \n\t"
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"slt %[r1], %[t0], %[max_q16] \n\t"
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"movz %[t1], %[max_q16], %[r0] \n\t"
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"movz %[t0], %[max_q16], %[r1] \n\t"
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#endif
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"addu %[offset], %[offset], %[ar_g_Q0] \n\t"
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#if defined(MIPS_DSP_R1_LE)
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"sra %[t1], %[t1], 16 \n\t"
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"sra %[t_ar], %[t_ar], 16 \n\t"
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#else
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"slt %[r0], %[t1], %[min_q16] \n\t"
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"slt %[r1], %[t0], %[min_q16] \n\t"
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"movn %[t1], %[min_q16], %[r0] \n\t"
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"movn %[t0], %[min_q16], %[r1] \n\t"
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"addu %[t_ar], $zero, %[t0] \n\t"
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#endif
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"sh %[t1], 0(%[offset]) \n\t"
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"bgtz %[count], 1b \n\t"
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" addiu %[count], %[count], -1 \n\t"
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"2: \n\t"
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"sh %[t_ar], 0(%[tmp]) \n\t"
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"sh %[t_ar], 0(%[ar_g_Q0]) \n\t"
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".set pop \n\t"
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: [t_ar] "=&r" (t_ar), [count] "+r" (count), [offset] "=&r" (offset),
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[r0] "=&r" (r0), [r1] "=&r" (r1), [r2] "=&r" (r2), [t0] "=&r" (t0),
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#if !defined(MIPS_DSP_R1_LE)
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[tmp_cth] "=&r" (tmp_cth), [tmp_sth] "=&r" (tmp_sth),
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[tmp_arg] "=&r" (tmp_arg),
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#endif
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[t1] "=&r" (t1), [t2] "=&r" (t2)
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: [tmp] "r" (&ar_f_Q0[n+1]), [cth_Q15] "r" (cth_Q15),
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#if !defined(MIPS_DSP_R1_LE)
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[max_q16] "r" (max_q16), [min_q16] "r" (min_q16),
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#endif
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[sth_Q15] "r" (sth_Q15), [ar_g_Q0] "r" (ar_g_Q0)
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: "memory", "hi", "lo"
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);
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}
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}
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// MIPS optimization of the inner loop used for function
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// WebRtcIsacfix_NormLatticeFilterMa(). It does:
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//
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// for 0 <= n < HALF_SUBFRAMELEN - 1:
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// *ptr2 = input2 * (*ptr2) + input0 * (*ptr0));
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// *ptr1 = input1 * (*ptr0) + input0 * (*ptr2);
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//
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// Note, function WebRtcIsacfix_FilterMaLoopMIPS and WebRtcIsacfix_FilterMaLoopC
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// are not bit-exact. The accuracy of the MIPS function is same or better.
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void WebRtcIsacfix_FilterMaLoopMIPS(int16_t input0, // Filter coefficient
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int16_t input1, // Filter coefficient
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int32_t input2, // Inverse coeff (1/input1)
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int32_t* ptr0, // Sample buffer
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int32_t* ptr1, // Sample buffer
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int32_t* ptr2) { // Sample buffer
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#if defined(MIPS_DSP_R2_LE)
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// MIPS DSPR2 version. 4 available accumulators allows loop unrolling 4 times.
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// This variant is not bit-exact with WebRtcIsacfix_FilterMaLoopC, since we
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// are exploiting 64-bit accumulators. The accuracy of the MIPS DSPR2 function
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// is same or better.
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int n = (HALF_SUBFRAMELEN - 1) >> 2;
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int m = (HALF_SUBFRAMELEN - 1) & 3;
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int r0, r1, r2, r3;
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int t0, t1, t2, t3;
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int s0, s1, s2, s3;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"1: \n\t"
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"lw %[r0], 0(%[ptr0]) \n\t"
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"lw %[r1], 4(%[ptr0]) \n\t"
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"lw %[r2], 8(%[ptr0]) \n\t"
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"lw %[r3], 12(%[ptr0]) \n\t"
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"mult $ac0, %[r0], %[input0] \n\t"
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"mult $ac1, %[r1], %[input0] \n\t"
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"mult $ac2, %[r2], %[input0] \n\t"
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"mult $ac3, %[r3], %[input0] \n\t"
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"lw %[t0], 0(%[ptr2]) \n\t"
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"extr_rs.w %[s0], $ac0, 15 \n\t"
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"extr_rs.w %[s1], $ac1, 15 \n\t"
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"extr_rs.w %[s2], $ac2, 15 \n\t"
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"extr_rs.w %[s3], $ac3, 15 \n\t"
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"lw %[t1], 4(%[ptr2]) \n\t"
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"lw %[t2], 8(%[ptr2]) \n\t"
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"lw %[t3], 12(%[ptr2]) \n\t"
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"addu %[t0], %[t0], %[s0] \n\t"
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"addu %[t1], %[t1], %[s1] \n\t"
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"addu %[t2], %[t2], %[s2] \n\t"
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"addu %[t3], %[t3], %[s3] \n\t"
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"mult $ac0, %[t0], %[input2] \n\t"
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"mult $ac1, %[t1], %[input2] \n\t"
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"mult $ac2, %[t2], %[input2] \n\t"
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"mult $ac3, %[t3], %[input2] \n\t"
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"addiu %[ptr0], %[ptr0], 16 \n\t"
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"extr_rs.w %[t0], $ac0, 16 \n\t"
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"extr_rs.w %[t1], $ac1, 16 \n\t"
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"extr_rs.w %[t2], $ac2, 16 \n\t"
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"extr_rs.w %[t3], $ac3, 16 \n\t"
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"addiu %[n], %[n], -1 \n\t"
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"mult $ac0, %[r0], %[input1] \n\t"
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"mult $ac1, %[r1], %[input1] \n\t"
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"mult $ac2, %[r2], %[input1] \n\t"
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"mult $ac3, %[r3], %[input1] \n\t"
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"sw %[t0], 0(%[ptr2]) \n\t"
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"extr_rs.w %[s0], $ac0, 15 \n\t"
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"extr_rs.w %[s1], $ac1, 15 \n\t"
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"extr_rs.w %[s2], $ac2, 15 \n\t"
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"extr_rs.w %[s3], $ac3, 15 \n\t"
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"sw %[t1], 4(%[ptr2]) \n\t"
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"sw %[t2], 8(%[ptr2]) \n\t"
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"sw %[t3], 12(%[ptr2]) \n\t"
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"mult $ac0, %[t0], %[input0] \n\t"
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"mult $ac1, %[t1], %[input0] \n\t"
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"mult $ac2, %[t2], %[input0] \n\t"
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"mult $ac3, %[t3], %[input0] \n\t"
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"addiu %[ptr2], %[ptr2], 16 \n\t"
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"extr_rs.w %[t0], $ac0, 15 \n\t"
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"extr_rs.w %[t1], $ac1, 15 \n\t"
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"extr_rs.w %[t2], $ac2, 15 \n\t"
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"extr_rs.w %[t3], $ac3, 15 \n\t"
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"addu %[t0], %[t0], %[s0] \n\t"
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"addu %[t1], %[t1], %[s1] \n\t"
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"addu %[t2], %[t2], %[s2] \n\t"
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"addu %[t3], %[t3], %[s3] \n\t"
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"sw %[t0], 0(%[ptr1]) \n\t"
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"sw %[t1], 4(%[ptr1]) \n\t"
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"sw %[t2], 8(%[ptr1]) \n\t"
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"sw %[t3], 12(%[ptr1]) \n\t"
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"bgtz %[n], 1b \n\t"
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" addiu %[ptr1], %[ptr1], 16 \n\t"
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"beq %[m], %0, 3f \n\t"
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" nop \n\t"
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"2: \n\t"
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"lw %[r0], 0(%[ptr0]) \n\t"
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"lw %[t0], 0(%[ptr2]) \n\t"
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"addiu %[ptr0], %[ptr0], 4 \n\t"
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"mult $ac0, %[r0], %[input0] \n\t"
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"mult $ac1, %[r0], %[input1] \n\t"
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"extr_rs.w %[r1], $ac0, 15 \n\t"
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"extr_rs.w %[t1], $ac1, 15 \n\t"
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"addu %[t0], %[t0], %[r1] \n\t"
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"mult $ac0, %[t0], %[input2] \n\t"
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"extr_rs.w %[t0], $ac0, 16 \n\t"
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"sw %[t0], 0(%[ptr2]) \n\t"
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"mult $ac0, %[t0], %[input0] \n\t"
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"addiu %[ptr2], %[ptr2], 4 \n\t"
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"addiu %[m], %[m], -1 \n\t"
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"extr_rs.w %[t0], $ac0, 15 \n\t"
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"addu %[t0], %[t0], %[t1] \n\t"
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"sw %[t0], 0(%[ptr1]) \n\t"
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"bgtz %[m], 2b \n\t"
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" addiu %[ptr1], %[ptr1], 4 \n\t"
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"3: \n\t"
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".set pop \n\t"
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: [r0] "=&r" (r0), [r1] "=&r" (r1), [r2] "=&r" (r2),
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[r3] "=&r" (r3), [t0] "=&r" (t0), [t1] "=&r" (t1),
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[t2] "=&r" (t2), [t3] "=&r" (t3), [s0] "=&r" (s0),
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[s1] "=&r" (s1), [s2] "=&r" (s2), [s3] "=&r" (s3),
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[ptr0] "+r" (ptr0), [ptr1] "+r" (ptr1), [m] "+r" (m),
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[ptr2] "+r" (ptr2), [n] "+r" (n)
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: [input0] "r" (input0), [input1] "r" (input1),
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[input2] "r" (input2)
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: "memory", "hi", "lo", "$ac1hi", "$ac1lo", "$ac2hi",
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"$ac2lo", "$ac3hi", "$ac3lo"
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);
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#else
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// Non-DSPR2 version of the function. Avoiding the accumulator usage due to
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// large latencies. This variant is bit-exact with C code.
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int n = HALF_SUBFRAMELEN - 1;
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int32_t t16a, t16b;
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int32_t r0, r1, r2, r3, r4;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"sra %[t16a], %[input2], 16 \n\t"
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"andi %[t16b], %[input2], 0xFFFF \n\t"
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#if defined(MIPS32R2_LE)
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"seh %[t16b], %[t16b] \n\t"
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"seh %[input0], %[input0] \n\t"
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"seh %[input1], %[input1] \n\t"
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#else
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"sll %[t16b], %[t16b], 16 \n\t"
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"sra %[t16b], %[t16b], 16 \n\t"
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"sll %[input0], %[input0], 16 \n\t"
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"sra %[input0], %[input0], 16 \n\t"
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"sll %[input1], %[input1], 16 \n\t"
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"sra %[input1], %[input1], 16 \n\t"
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#endif
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"addiu %[r0], %[t16a], 1 \n\t"
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"slt %[r1], %[t16b], $zero \n\t"
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"movn %[t16a], %[r0], %[r1] \n\t"
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"1: \n\t"
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"lw %[r0], 0(%[ptr0]) \n\t"
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"lw %[r1], 0(%[ptr2]) \n\t"
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"addiu %[ptr0], %[ptr0], 4 \n\t"
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"sra %[r2], %[r0], 16 \n\t"
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"andi %[r0], %[r0], 0xFFFF \n\t"
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"mul %[r3], %[r2], %[input0] \n\t"
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"mul %[r4], %[r0], %[input0] \n\t"
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"mul %[r2], %[r2], %[input1] \n\t"
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"mul %[r0], %[r0], %[input1] \n\t"
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"addiu %[ptr2], %[ptr2], 4 \n\t"
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"sll %[r3], %[r3], 1 \n\t"
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"sra %[r4], %[r4], 1 \n\t"
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"addiu %[r4], %[r4], 0x2000 \n\t"
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"sra %[r4], %[r4], 14 \n\t"
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"addu %[r3], %[r3], %[r4] \n\t"
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"addu %[r1], %[r1], %[r3] \n\t"
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"sra %[r3], %[r1], 16 \n\t"
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"andi %[r4], %[r1], 0xFFFF \n\t"
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"sra %[r4], %[r4], 1 \n\t"
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"mul %[r1], %[r1], %[t16a] \n\t"
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"mul %[r3], %[r3], %[t16b] \n\t"
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"mul %[r4], %[r4], %[t16b] \n\t"
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"sll %[r2], %[r2], 1 \n\t"
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"sra %[r0], %[r0], 1 \n\t"
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"addiu %[r0], %[r0], 0x2000 \n\t"
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"sra %[r0], %[r0], 14 \n\t"
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"addu %[r0], %[r0], %[r2] \n\t"
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"addiu %[n], %[n], -1 \n\t"
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"addu %[r1], %[r1], %[r3] \n\t"
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"addiu %[r4], %[r4], 0x4000 \n\t"
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"sra %[r4], %[r4], 15 \n\t"
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"addu %[r1], %[r1], %[r4] \n\t"
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"sra %[r2], %[r1], 16 \n\t"
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"andi %[r3], %[r1], 0xFFFF \n\t"
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"mul %[r3], %[r3], %[input0] \n\t"
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"mul %[r2], %[r2], %[input0] \n\t"
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"sw %[r1], -4(%[ptr2]) \n\t"
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"sra %[r3], %[r3], 1 \n\t"
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"addiu %[r3], %[r3], 0x2000 \n\t"
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"sra %[r3], %[r3], 14 \n\t"
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"addu %[r0], %[r0], %[r3] \n\t"
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"sll %[r2], %[r2], 1 \n\t"
|
|
"addu %[r0], %[r0], %[r2] \n\t"
|
|
"sw %[r0], 0(%[ptr1]) \n\t"
|
|
"bgtz %[n], 1b \n\t"
|
|
" addiu %[ptr1], %[ptr1], 4 \n\t"
|
|
".set pop \n\t"
|
|
: [t16a] "=&r" (t16a), [t16b] "=&r" (t16b), [r0] "=&r" (r0),
|
|
[r1] "=&r" (r1), [r2] "=&r" (r2), [r3] "=&r" (r3),
|
|
[r4] "=&r" (r4), [ptr0] "+r" (ptr0), [ptr1] "+r" (ptr1),
|
|
[ptr2] "+r" (ptr2), [n] "+r" (n)
|
|
: [input0] "r" (input0), [input1] "r" (input1),
|
|
[input2] "r" (input2)
|
|
: "hi", "lo", "memory"
|
|
);
|
|
#endif
|
|
}
|